Selective signalling apparatus with storage of call signals

ABSTRACT

Selective calling apparatus for use in electronic equipment, such as a radio pager, for disabling an audio calling device and storing the calling information so that it can be reproduced when desired. This prevents the interruption of a person carrying the pager, such as a doctor in surgery, who does not want to be disturbed, and permits the person to receive the call at his convenience by operation of a switch. The storage or memory circuit disables the audio stage which produces the call tone and holds the signal in a decoder which responds to the code signal so that the call can be produced when the memory circuit is reset.

United States Patent 1 Nickerson 1-111, 3,742,481 1 June 26, 1973SELECTIVE SIGNALLING APPARATUS WITH STORAGE 0F CALL SIGNALS Douglas W.Nickerson, North Miami Beach, Fla.

Assignee: Motorola, Inc., Franklin Park, 111.

Filed: Dec. 6, 1971 Appl. No.1 205,071

lnventor:

U.S. CI. 340/311 R, 340/171 R, 340/164 R Int. Cl. I'I04m 11/02 Field ofSearch 340/311 R, 312 R,

References Cited UNITED STATES PATENTS 3,510,864 5/1970 McDonald 340/311R RECEIVER RADIO 34 g' il THRESHOL6 FILTER I DETECTOR 39 l 48 Q fTHRESHOLD FLTER DETECTOR T I 60 ASTABLE 49]: 5O 62 l T PrimaryExamirierHarold l. Pitts Attorney- Foorman ll. Mueller. (ieorge Aichcleet al.

[57] ABSTRACT Selective calling apparatus for use in electronicequipment, such as a radio pager, for disabling an audio call- 'ingdevice and storing the calling information so that it can be reproducedwhen desired. This prevents the interruption of a person carrying thepager, such as a doctor in surgery, who does not want to be disturbed,and permits the person to receive the call at his convenience byoperation of a switch. The storage or'memory circuit disables the audiostage which produces the call tone and holds the signal in a decoderwhich responds to the code signal so that the call can be produced whenthe memory circuit is reset.

10 Claims, 2 Drawing Figures BACKGROUND OF THE INVENTION This inventionrelates generally to electronic circuits for storing a call signal, andmore particularly to such a circuit used with a pager having an' audiostage and a decoder for providing a call tone, and which disables theaudio stage and holds the decoder operative until the circuit is reset.

In various selective calling systems, such as radio pagers, whichproduce an audio call tone, it is desirable in some cases to prevent theaudio call tone. from sounding. For example, pagers are worn by doctors,and when the doctor is caring for a patient he does not want to beinterrupted by the call tone. It is desired, however, that as soon asthe doctor is in a position to receive the call, he is able tointerrogate the system to determine if he has been called. In the past,the only provision to prevent the audio call tone from sounding was toturn off the pager. In such case, any message which comes in while thepager is off will be lost, and there is no indication that a call hasbeen received.

Although recording or storage devices are known which can retaininformation as to a call, these have been too large to provide within apager, which is of a size to be carried by a person, as in a pocket oron a belt. Known devices require additional equipment which consumespower and causes objectionable current drain in a small device having aself-contained battery. Also, such devices have been relativelyexpensive, to substantially increase the cost of the selective callingdevice involved. a

. SUMMARY or THE INVENTION It is an object of the present invention toprovide a selective calling system which acts to disable an audio toneor other calling device and to store the calling information so that itcan be produced upon interrogation.

Another object of the invention is to provide a memory circuit for aradio pager'having a decoder for procontinuously produce the outputsignal. This includes a first portion which operates without a delay sothat a call is not lost, and a second portion which operates after adelay to hold the decoder operative after the audio amplifier isenabled. A reset switch coupled to 'the memory circuit operates the sameto render the BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematicdiagram of a paging receiver including the memory circuit of theinvention; and

FIG. 2 is a circuit diagram of the memory circuit of FIG. 1.

DETAILED DESCRIPTION Referring now to the drawings, in FIG. 1 there isillustratedthe signalling system of the invention as utilized in apaging receiver. The receiver includes an antenna 10, and receivercircuits 12 for amplifying and detecting signals therefrom. The receivercircuits may be of known construction, and the signals may include audiosignals which appear on conductor 14 and tone signals which appear oncondutor 15. Alternatively, the receiver may be used to reproduce tonesignals only.

The audio signals are applied to audio amplifier 16 I which may includeamplifier stages 18, 20 and 22. The

output of amplifier stage 22 is applied to an audio transducer 24 whichmay be a miniature loudspeaker for providing the audio sound requiredfrom a pager or other small radio receivenThe amplifier stages 18, 20and 22 are selectively energized by a potential supplied from terminal26 through regulator 28 to the amplifier stages. The regulator iscontrolled by a potential applied thereto from OR gate 30, as will beexplained.

a The amplifier and regulator may be of the type deducing a callingsignal in response to a particular received code signal, wherein thememory circuit requires only a small number of parts and consumes littlepower to hold the decoder operative to retain the calling signal untilreset.

A further object of the invention is to provide a radio pager havingaduio stages for producing an audio calling tone with a simple andinexpensive memory circuit operative to be set to disable the audiostages and retain the calling signal, and to be reset to enable theaudio stages and apply the calling signal thereto.

In practicing the invention, a radio pager is provided which includes adecoder which responds to a calling signal including two tone providedin sequence, and which has a tone oscillator actuated by the decoder andan audio amplifier and transducer for producing an audible tone inresponse to the tone oscillations. Theaudio amplifier may also be usedto amplify information signals. A memory or storing circuit is coupledto the decoder through a switch and to the audio amplifier. The memorycircuit has a first portion for disabling the audio amplifier when thedecoder provides an output signal, so that the tone oscillations fromthe decoder are not reproduced. A secondportion of the memory circuitholds the decoder in a condition to scribed in copending applicationSer. No. 151,461, filed June 9, 1971 by John R. Rezek, entitledControllable Audio Amplifier for Miniature Receiver Provided by a ThickFilm-Module Including an Integrated Circuit. The tone output of thereceiver circuits 12 on conductor 15 is applied through capacitor 32 toactivate filters 34 and 36 for selecting the A and B tones,respectively. The selective code used may include a first A tonefollowed by a second B tone and the filters select the tones from othersignals which may be present and apply the same to decoder 35. The Atone is applied to detector 38, which acts to discharbe capacitor 39,which is normally charged from the supply potential through resistor 40.At the termination of the A tone, capacitor 39 will charge to triggerinverter 42 to discharge capacitor-43 very rapidly. The negative goingvoltage across capacitor 43 is coupled by capacitor 44 to inverter 45,providing a low input thereto. This input will stay low until capacitors44 and 43 charge from the supply potential through resistor 41. The lowinput to inverter 45 will provide a high input to AND gate 46. Tone Amust be received for a predetermined time to discharge capacitor 39 to agiven level and this provides protection with respect to undesired shortduration signals of the frequency of tone A. The high input to AND gate46 is delayed by the charge of capacitor 39 and the discharge ofcapacitor 43.

Similarly, threshold detector 48 responds to the B tone, and acts todischarge capacitor 49, which is normally charged through resistor 50.The voltage across capacitor 49 is applied through inverter 52 and ORgate 54 to the second input of AND gate 46. When the B tone is receivedduring the time period following the A tone that a high input is appliedfrom inverter 45 to AND gate 46, this AND gate will operate to provide adirect current potential on the output conductor 56. This is appliedthrough resistor 58 and conductor 59 to one input of OR gate 30 of theaudio amplifier l6'to turn on the regulator 28 so that the audioamplifier is rendered operative. The output on conductor 56 is alsoapplied through inverter 57 to the input of inverter 45. This maintainsthe first input to AND gate 46 as long as the AND gate 46 provides anoutput. This will cause the AND gate 46 to remain operated as long asthe B tone is received.

The output of AND gate 46 on conductor 56 is also applied to astablecircuit 60 of the decoder 35. This applies an output through inverter 62to AND gate 64 to which the output from conductor 56 is also applied.

Accordingly, AND gate 64 will operate intermettently to activate tomeoscillator 66, which applies tone signals through condutor 68 to theinput of audio amplifier stage 20. This tone signal is amplified instages and 22 and reproduced by loudspeaker 24.

When the decoder is used in a pager for tone only operation, the decoderoutput on conductor 56 is also applied through resistor 70 and capacitor71 to conductor 69 connected to the second input of OR gate 54. Thiswill act to apply a potential to the second input of AND gate 46 for atime after the B tone terminates. Accordingly, the decoder will causethe tone oscillator 66 to. operate as long as the B tone is received,and for an additional time determined by the values of resistor 70 andcapacitor 71.

The decoder 35 may be in accordance with the decoder described inapplication Ser. No. 151,460, filed June 9, 197i by Raymond J.Millington and John R. Rezek, entitled, Integrated Circuit DecoderResponsive to Two Sequential Tones with Group Call Provisions."

A memory or storing circuit 75 is coupled to the audio amplifier 16 anddecoder 35, and has a terminal 76 connected to the conductor 56providing the output of decoder 35. This terminal is connected throughswitch 78 and conductor 79 to the base of transistor 80. The emitter oftransistor 80 is connected to ground, and the collector is connected toconductor 59, which is connected to one input of the OR gate of theaudio amplifier 16. Accordingly, when the switch 78 is closed, and thedecoder provides an output at conduc tor 56, this potential applied tothe base of transistor 80 will render the same conducting to groundconductor 59, so that an actuating potential cannot be appliedtherethrough to the OR gate 30 to turn on the regulator 28. This acts tohold the audio circuit disabled when the decoder responds to the callingcode.

The potential applied to conductor 79 from the decoder is also appliedto one input of AND gate 82. Inverter 84 normally provides a second highinput to AND gate 82 so that this AND gate produces a positive output.The output is applied through conductor 85 to conductor 69 connected tothe second input of OR gate 54 of the decoder 35, to hold the sameoperated in the absence of the B tone. This causes AND gate 46 tocontinue to provide the output on conductor 56, as long as switch 78 isclosed and AND gate 82 produces an output.

The potential on conductor 79 of the memory circuit is also applied tothe input of AND gate 86. The second input to the AND gate 86 isconnected to point 97, which is connected to the audio amplifier 16.Point 97 is connected within audio amplifier 16 through resistor 98 tothe positive potential at terminal 26, and provides a high input so thatAND gate 86 is operative to apply a potential to delay circuit 88. Thisacts to render transistor conductive after a given delay, such as twoseconds. Transistor 90 provides a ground on conductor 92 which extendsto the inverter 52, and this provides a high .input to the OR gate 54.Accordingly, the memory circuit 75 applies a second input to OR gate 54,which is delayed with respect to the input applied thereto fromconductor 69. This input applied through OR gate 54 to AND gate 46 willhold AND gate 46 operated for a period of time after the input fromconductor 69 terminates.

The memory circuit has a reset switch which when operated applies groundto the emitter of transistor 96, so that transistor 96 conducts andgrounds point 97. This point is coupled to inverter 99, which isconnected to a second input of the OR gate 30 of the audio amplifier 16.This inverter provides a high output which is applied through OR gate 30to actuate the regulator 28 to energize the amplifier. The amplifier 16is, therefore, turned on even though switch 78 is still closed andcondoctor 59 is grounded by transistor 80.

The ground potential at point 97 is also applied to the second input ofAND gate 86 and to the input of inverter 87. The output of AND gate 86therefore drops to a low level to remove the input to delay circuit 88,and the inverter 87 produces a positive output which resets the delaycircuit. This immediately moves the bias to transistor 90 so that itceases to conduct. This removes the ground on conductor 92 which latchesthe decoder 35. Capacitor 49 then charges through resistor 50 to providea positive potential to the inverter 52.

When reset switch 95 is released, transistor 96 is ren' derednonconducting, and point 97 returns to a high potential. This triggersone shot pulse generator to produce an output which is applied toinverter 84. The inverter produces a low output for the two secondperiod of generator 100, to remove the second input to AND gate 82. Thiscauses the output of gate 82 to go low to remove the clamp potentialapplied through conductor 85 to the second input of OR gate 54. Thisdeactivates the decoder, and the output at conductor 56 terminates toprovide a low input to OR gate 30. As point 97 is at the supplypotential, inverter 99 provided a low input to OR gate 30, so that bothinputs are low and the regulator turns off to deenergize the amplifier16.

The switch 78 may be part of the main operating switch for the pager,which has a plurality of positions, one to turn off the pager, a secondto turn on the pager so that it receives normal calls, and a third,provided by contacts 78, which provides the memory action. Contacts 78are opened when the pager switch is operated to the on position forreceiving normal calls. This removes the potential conductors 79 andrenders transistor 80 nonconducting to remove the audio clamp, so

that the audio circuit operates to reproduce the audible alert tone fromoscillator 66 of the decoder. This also disables AND gate 82 to removethe potential on conductor 85, but the potential on conductor 69connected to the second input of gate 54 is held for a short time byaction of capacitor 71 and resistors 70, 72 and 73. AND gate 86 is alsodisabled to render transistor 92 nonconducting after the delay producedby circuit 88.

This causes the stored call to be reproduced by operating the pagerswitch to the on position, as well as by operatingthe momentary resetswitch 95. The main pager switch can be a three position slide switch,and the reset switch can be coupled thereto so that it is operated whenthe slide switch operating. member is depressed, for example.

The system which has been described in connection with FIG. 1 is for usein tone operation radio pagers.

That is, in radio pagers which provide a tone to. indicate to the personcarrying the pager that a message is being held for him. He must go to atelephone to call his office, or some other number, to find what themessage is. Radio pagers are also provided which provide tone and voiceoperation. In such pagers, an alert tone of short-duration is producedfollowed by an audio message. In the tone operation pagers, it isdesired to provide the alert tone for the relatively long period toinsure that the person carrying the pager hears the same. Accordingly,the resistor 70 and capacitor 71 are provided to hold the decoder outputon for a time after the termination of the calling code. In tone andvoice pagers, it is not desired to hold the alert tone on beyond thecalling code, as the voice message follows the calling code and if thealert tone is continued it will inter- 'fere with the voice message.

For the above reasons, in tone and voice radio pagers, the resistor 70and capacitor71 are omitted. In such pagers, capacitor 74 is connectedto conductor 69 to provide a short delay after the potential onconductor 85 from the memory circuit is removed. This will hold thedecoder output on conductor 56 for a short time. Also in tone and voicepagers, the reset switch 95 is not used and switch 102 is used. Switch102 directly grounds point 97 to reset the memory circuit and terminatethe ground potential on conductor 92 which latches the decoder. Thismakes it possible to monitor the channel in tone and voice pagers.

In FIG. 2 there is shown a circuit diagram of the memory circuit 75 ofFIG. 1. The circuit provides the same functions described in connectionwith the block diagram of FIG. 1, and corresponding parts are given thesame numbers. The input terminal 76 receives the direct current outputof the decoder 35, and the connection through switch 78 and conductor 79to transistor 80, which grounds conductor 59, is exactly the same as inFIG. 1.

96, the emitter of which is connected to ground through switch 95.Transistor 96 and switch 95 are exactly the same as in FIG. 1.'

The one shot pulse generator 100 in FIG. 1 is formed by transistors 110and 112 and the circuit elements connected thereto. Capacitor 114controls the time duration of the pulse. Transistor 118 forms theinverter coupling the pulse generator to the second input of the ANDgate 82, which is formed by transistor 108, as pre viously stated.During normal operation, capacitor 114 charges through resistor 115 andresistor 98, which is connected to the supply potential terminal 26.This applies a potential to the base of transistor 118 which rendersthesame conducting, and this grounds the base of transistor 108 so thattransistor 108 is cut off. Accordingly, transistor 108 is normally offand the output on I of transistor 112 to render transistor 112conducting.

Transistors 105 and 106, which are rendered conducting by the potentialon conductor 79, form half of the AND gate 82 in FIG. 1. Transistor 108forms the other half of the AND gate 82. Transistor 108, when Thisgrounds capacitor 114 so that it is discharged. This is provided so thatif the pager had been turned off, and i then quickly turned onagain,-the capacitor 114 might retain a charge. Accordingly, for a shorttime when the pager is first turned on, transistor 108 will be renderedconducting so that line will be at ground potential and cannot latch thedecoder 35. This is desired because the decoder is arranged to produce atone when the pager is first turned on so that the person using thepager knows that it is operative. However, it is not desired to storethis operation, which is not in response to a paging call. Transistorwill be rendered conducting to ground the base of transistor 112, sothat it can conduct for only a very short period. Then capacitor 114will charge and render transistor 118 conducting to cut off transistor108.

The above operation makes it possible to reset the memory circuit by amomentary operation of switch 95. This grounds point 97, and when theground is removed the potential applied acts to short capacitor 114, asdescribed to release the latch on decoder 35.

Capacitor 120 forms the delay circuit 88 (FIG. 1) which controls theconductivity of transistor 90. Capacitor 120 is charged through resistor121 when the potential is present on conductor 79, derived from thedecoder 35. When there is no potential on conductor 79, capacitor 120discharges through resistors 121 and 122. The second input to the ANDgate 86 and the reset of the delay .circuit 88 (FIG. 1) are, in effect,pro-' vided by. transistors 124 and 125 which are connected from point97 to capacitor 120. As point 97 is normally high, transistor 124 isnormally conducting to hold transistor 125 out off. This allowscapacitor 120 to charge to render transistor 92 conducting when there isa potential from decoder 35 on conductor 79. As previously stated, sometime will be required for capacitor 120 to charge and turn on transistor90. Accordingly, the latch for thedecoder provided by conductor 92 isdelayed with respect to the latch provided by conductor 85.

When the reset switch 95 is operated and point 97 is pulled to groundpotential, transistor 124 will be cut off and transistor 125 will berendered conducting. This will discharge capacitor 120, and after thetime required for the charge to drop to a predetermined level(essentially zero), transistor 90 will be turned off. This leased untilreset switch 95 is released, or switch 78 is opened.

The memory circuit which has been described has been found to be highlyeffective to store a call when it is desired that an alert tone not besounded. The memory circuit is of simple construction, requiring arelatively small number of components and a very small amount of spacein the pager device. Since the memory circuit latches the decoder sothat it stores the message, separate storage means is not required. Thememory circuit requires a minimum of power which is extremely importantin a small radio pager having a selfcontained battery. A further savingin power can be obtained by latching the astable circuit 60 in the statewhich holds the tone oscillator 66 off, in the system of FIG. 1. Thiscan be accomplished by the coupling of conductor 92 which provides alatching potential to the astable circuit. This will eliminate thecurrent drain required by the tone oscillator during the memory period.

I claim:

1. In selective signalling apparatus including a decoder for. producingan output signal in response to a particular code signal and which isadapted to be latched to maintain the output signal by the applicationof a latching signal thereto, and including alerting means coupled tothe decoder and adapted to be operated by the output signal therefrom,and further adapted tobe disabled by application of a signal thereto,the combination including:

first means coupled to the decoder for receiving the output signaltherefrom,

second means coupled to said first means and to the alerting means andresponsive to the decoder output signal for applying a signal to thealerting means for disabling the same,

third means coupled to said first means and to the decoder andresponsive to the decoder output signal .coder output signal forterminating the response of said second means thereto, and for operatingsaid third means to release the decoder.

3. The combination of claim 1 wherein said reset means includes switchmeans for operating said third means to release the decoder and to resetsaid third means for a further operation.

4. The combination of claim 3 wherein said switch means has first andsecond positions, with said first position of said switch meansoperating said third means to release the decoder, and said secondposition of said switch means operating said third means to reset thesame.

5. The combination of claim 1 wherein said third means includes a firstportion coupled to the decoder and having means operative withoutsubstantial delay to hold the decoder operative, and a second portioncoupled to the decoder and having means operative after a given delay tohold the decoder operative.

6. The combination of claim 5 wherein said first means includes switchmeans to terminate the application of the decoder output signal to saidthird means, whereby said first portion releases the decoder withoutsubstantial delay, and said second portion releases the decoder afterthe given delay.

7. The combination of claim 5 wherein said reset means is coupled tosaid first and second portions of said third means and operates the sameto release the decoder without substantial delay.

8. The combination of claim 1 wherein said second means includes aportion coupled to said reset means for rendering the alerting meansoperative.

9. The combination of claim 8 wherein said portion of said second-meansis an OR gate having first and second inputs, with means applying thedecoder output signal to said first input, means for disabling saidfirst input in response to the decoder output signal, and means coupledto said reset means and to said second input for applying a signal tosaid second input in response to operation of said reset means to renderthe alerting means operative.

10. The combination of claim 9 wherein said first means includes switchmeans for interrupting the decoder output signal for terminating theresponse of said second means thereto to enable said first input of saidOR gate.

ass s s

1. In selective signalling apparatus including a decoder for producingan output signal in response to a particular code signal and which isadapted to be latched to maintain the output signal by the applicationof a latching signal thereto, and including alerting means coupled tothe decoder and adapted to be operated by the output signal therefrom,and further adapted to be disabled by application of a signal thereto,the combination including: first means coupled to the decoder forreceiving the output signal therefrom, second means coupled to saidfirst means and to the alerting means and responsive to the decoderoutput signal for applying a signal to the alerting means for disablingthe same, third means coupled to said first means and to the decoder andresponsive to the decoder output signal from said first means forapplying a latching signal to the decoder to latch the same and therebymaintain the output signal, and reset mEans coupled to said third meansto reset the same and remove said latching signal.
 2. The combination ofclaim 1 wherein said first means includes switch means for interruptingthe decoder output signal for terminating the response of said secondmeans thereto, and for operating said third means to release thedecoder.
 3. The combination of claim 1 wherein said reset means includesswitch means for operating said third means to release the decoder andto reset said third means for a further operation.
 4. The combination ofclaim 3 wherein said switch means has first and second positions, withsaid first position of said switch means operating said third means torelease the decoder, and said second position of said switch meansoperating said third means to reset the same.
 5. The combination ofclaim 1 wherein said third means includes a first portion coupled to thedecoder and having means operative without substantial delay to hold thedecoder operative, and a second portion coupled to the decoder andhaving means operative after a given delay to hold the decoderoperative.
 6. The combination of claim 5 wherein said first meansincludes switch means to terminate the application of the decoder outputsignal to said third means, whereby said first portion releases thedecoder without substantial delay, and said second portion releases thedecoder after the given delay.
 7. The combination of claim 5 whereinsaid reset means is coupled to said first and second portions of saidthird means and operates the same to release the decoder withoutsubstantial delay.
 8. The combination of claim 1 wherein said secondmeans includes a portion coupled to said reset means for rendering thealerting means operative.
 9. The combination of claim 8 wherein saidportion of said second means is an OR gate having first and secondinputs, with means applying the decoder output signal to said firstinput, means for disabling said first input in response to the decoderoutput signal, and means coupled to said reset means and to said secondinput for applying a signal to said second input in response tooperation of said reset means to render the alerting means operative.10. The combination of claim 9 wherein said first means includes switchmeans for interrupting the decoder output signal for terminating theresponse of said second means thereto to enable said first input of saidOR gate.